5SGXEA7N2F45C1N
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FPGA Stratix V GX 622K Cells 28nm 1932-Pin FC-FBGA 14.1Gbps Transceivers
Дополнительная информация
Field Programmable Gate Array (FPGA) with 622,000 logic cells and 939,000 registers, built on 28nm process technology. Features 512 18x18 multipliers, 256 dedicated DSP blocks, and 51200 Kbit RAM. Supports up to 840 user I/Os, 48 transceiver blocks operating at 14.1 Gbps, and 4 PCI blocks. This surface-mount device utilizes a 1932-pin FC-FBGA package with a 1mm pin pitch.
| PCB | 1932 |
| ECCN | 3A001.a.7.a |
| PPAP | No |
| Jedec | MS-034AAW-1 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Mounting | Surface Mount |
| RAM Bits | 51200Kbit |
| Cage Code | 4BA62 |
| Pin Count | 1932 |
| Automotive | No |
| Lead Shape | Ball |
| PCI Blocks | 4 |
| Schedule B | 8542390000 |
| Family Name | Stratix® V GX |
| Speed Grade | 1 |
| Package/Case | FC-FBGA |
| AEC Qualified | No |
| Dedicated DSP | 256 |
| Ethernet MACs | 2 |
| RoHS Versions | 2011/65/EU, 2015/863 |
| Pin Pitch (mm) | 1 |
| Programmability | Yes |
| Package Material | Plastic |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|SPAUI MAC|RLDRAM II Controller Core|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB) |
| Transceiver Speed | 14.1Gbps |
| Basic Package Type | Ball Grid Array |
| Device Logic Cells | 622000 |
| Package Width (mm) | 45 |
| Process Technology | 28nm |
| Transceiver Blocks | 48 |
| Number of Registers | 939000 |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 2.7 |
| Package Length (mm) | 45 |
| Program Memory Type | SRAM |
| Number of Multipliers | 512 (18x18) |
| Seated Plane Height (mm) | 3.2 |
| External Memory Interface | DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | 0°C |
| Total Number of Block RAM | 2560 |
| Device Number of DLLs/PLLs | 28 |
| Maximum Number of User I/Os | 840 |
| Supported IP Core Manufacture | Altera/Barco Silex/Mobiveil, Inc/Commsonic |
| Differential I/O Standards Supported | LVPECL|LVDS|HCSL |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
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