5SGXMA7H2F35C2N
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Краткое описание:
FPGA Stratix V GX 622K Cells 28nm 1152-Pin FC-FBGA 14.1Gbps Transceiver
Дополнительная информация
Field-Programmable Gate Array (FPGA) with 622,000 logic cells and 939,000 registers, built on 28nm process technology. Features 552 user I/Os, 51200 Kbit RAM, 256 dedicated DSP blocks, and 4 PCI blocks. Includes 2 Ethernet MACs and 48 transceiver blocks operating at 14.1 Gbps. Packaged in a 1152-pin FC-FBGA (35x35mm) for surface mounting. Supports various external memory interfaces including DDR2, DDR3, RLDRAM II/III, and QDRII+SRAM.
| PCB | 1152 |
| ECCN | 3A001.a.7.a |
| PPAP | No |
| Jedec | MS-034AAR-1 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Mounting | Surface Mount |
| RAM Bits | 51200Kbit |
| Cage Code | 4BA62 |
| Pin Count | 1152 |
| Automotive | No |
| Lead Shape | Ball |
| PCI Blocks | 4 |
| Schedule B | 8542390000 |
| Family Name | Stratix® V GX |
| Speed Grade | 2 |
| Package/Case | FC-FBGA |
| AEC Qualified | No |
| Dedicated DSP | 256 |
| Ethernet MACs | 2 |
| RoHS Versions | 2011/65/EU, 2015/863 |
| Pin Pitch (mm) | 1 |
| Programmability | Yes |
| Package Material | Plastic |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|SPAUI MAC|RLDRAM II Controller Core|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB) |
| Transceiver Speed | 14.1Gbps |
| Basic Package Type | Ball Grid Array |
| Device Logic Cells | 622000 |
| Package Width (mm) | 35 |
| Process Technology | 28nm |
| Transceiver Blocks | 48 |
| Number of Registers | 939000 |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 2.9 |
| Package Length (mm) | 35 |
| Program Memory Type | SRAM |
| Number of Multipliers | 512 (18x18) |
| Seated Plane Height (mm) | 3.4 |
| External Memory Interface | DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | 0°C |
| Total Number of Block RAM | 2560 |
| Device Number of DLLs/PLLs | 28 |
| Maximum Number of User I/Os | 552 |
| Supported IP Core Manufacture | Altera/Barco Silex/Mobiveil, Inc/Commsonic |
| Differential I/O Standards Supported | LVPECL|LVDS|HCSL |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
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