CD4027BF3A
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Краткое описание:
Dual J-K Flip-Flop, CMOS, 24MHz, 18V, CDIP
Дополнительная информация
CMOS Dual J-K Master-Slave Flip-Flop featuring positive edge clock triggering. This integrated circuit offers two independent flip-flop elements, each with a maximum operating frequency of 24MHz. It operates across a supply voltage range of 3V to 18V and supports through-hole mounting in a CDIP package with tin-lead contact plating. Key electrical characteristics include a quiescent current of 20uA, a high-level output current of -4.2mA, and a low-level output current of 4.2mA, with a propagation delay of 400ns.
| RoHS | Not CompliantNo |
| Mount | Through Hole |
| Polarity | Non-Inverting |
| Frequency | 24MHz |
| Lead Free | Contains Lead |
| Packaging | Rail/Tube |
| Technology | CMOS |
| Output Type | TTL |
| Package/Case | CDIP |
| Max Frequency | 24MHz |
| Number of Bits | 2 |
| RoHS Compliant | No |
| Contact Plating | Tin, Lead |
| Propagation Delay | 400ns |
| Quiescent Current | 20uA |
| Max Supply Voltage | 18V |
| Min Supply Voltage | 3V |
| Number of Elements | 2 |
| Turn-On Delay Time | 400ns |
| Radiation Hardening | No |
| Clock Edge Trigger Type | Positive Edge |
| Low Level Output Current | 4.2mA |
| High Level Output Current | -4.2mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
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