CD54AC112F3A
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Краткое описание:
Dual JK Flip-Flop, Neg Edge Triggered, 100MHz, CDIP, 1.5-5.5V
Дополнительная информация
Dual negative edge-triggered J-K flip-flops with set and reset functionality. Features a 100MHz maximum operating frequency and operates across a wide temperature range of -55°C to 125°C. This CMOS logic IC supports a supply voltage from 1.5V to 5.5V, with a high-level output current of -24mA and a low-level output current of 24mA. The component is housed in a CDIP package for through-hole mounting and exhibits a propagation delay of 153ns.
| RoHS | Not CompliantNo |
| Mount | Through Hole |
| Polarity | Non-Inverting |
| Frequency | 100MHz |
| Lead Free | Contains Lead |
| Packaging | Rail/Tube |
| Technology | CMOS |
| Package/Case | CDIP |
| Max Frequency | 100MHz |
| Logic Function | JK-Type |
| Number of Bits | 2 |
| RoHS Compliant | No |
| Contact Plating | Tin, Lead |
| Propagation Delay | 153ns |
| Quiescent Current | 4uA |
| Max Supply Voltage | 5.5V |
| Min Supply Voltage | 1.5V |
| Number of Elements | 2 |
| Turn-On Delay Time | 153ns |
| Radiation Hardening | No |
| Clock Edge Trigger Type | Negative Edge |
| Low Level Output Current | 24mA |
| High Level Output Current | -24mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
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