CD54HC107F3A
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Dual J-K Flip-Flop, CMOS, 60MHz, Neg-Edge Trigger, CDIP
Дополнительная информация
Dual negative-edge triggered J-K flip-flops with reset, featuring CMOS technology and a maximum operating frequency of 60MHz. This integrated circuit offers a propagation delay of 255ns and operates within a supply voltage range of 2V to 6V. Designed for through-hole mounting in a CDIP package, it provides 5.2mA of output current at both high and low levels. The component supports a wide operating temperature range from -55°C to 125°C.
| RoHS | Not CompliantNo |
| Mount | Through Hole |
| Polarity | Non-Inverting |
| Frequency | 60MHz |
| Lead Free | Contains Lead |
| Packaging | Rail/Tube |
| Technology | CMOS |
| Package/Case | CDIP |
| Max Frequency | 60MHz |
| Logic Function | JK-Type |
| Number of Bits | 2 |
| RoHS Compliant | No |
| Contact Plating | Tin, Lead |
| Propagation Delay | 255ns |
| Quiescent Current | 4uA |
| Max Supply Voltage | 6V |
| Min Supply Voltage | 2V |
| Number of Elements | 2 |
| Turn-On Delay Time | 255ns |
| Radiation Hardening | No |
| Clock Edge Trigger Type | Negative Edge |
| Low Level Output Current | 5.2mA |
| High Level Output Current | -5.2mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
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