CD74HC73EE4
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Краткое описание:
Dual JK Flip-Flop, CMOS, Neg-Edge, 60MHz, 14-PDIP
Дополнительная информация
Dual negative-edge-triggered J-K flip-flops with reset, operating at up to 60MHz. This CMOS logic component features two independent J-K flip-flops, each with a single-ended input and non-inverting output. Designed for through-hole mounting in a PDIP package, it offers a wide operating temperature range from -55°C to 125°C and supports supply voltages from 2V to 6V. With a propagation delay of 160ns and a low quiescent current of 4uA, this RoHS compliant component is suitable for high-speed digital applications.
| RoHS | Compliant |
| Mount | Through Hole |
| Series | 74HC |
| Weight | 0.032734oz |
| Polarity | Non-Inverting |
| Frequency | 60MHz |
| Lead Free | Lead Free |
| Packaging | Rail/Tube |
| Input Type | SINGLE-ENDED |
| Technology | CMOS |
| Package/Case | PDIP |
| Logic Function | Flip-Flop, JK-Type |
| Number of Bits | 2 |
| Output Current | 5.2mA |
| RoHS Compliant | Yes |
| Contact Plating | Gold |
| Package Quantity | 25 |
| Propagation Delay | 160ns |
| Quiescent Current | 4uA |
| Max Supply Voltage | 6V |
| Min Supply Voltage | 2V |
| Number of Circuits | 2 |
| Number of Elements | 2 |
| Turn-On Delay Time | 13ns |
| Number of Input Lines | 2 |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Negative Edge |
| Low Level Output Current | 5.2mA |
| High Level Output Current | -5.2mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
| Number of Bits per Element | 1 |
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