CY7C1268XV18-633BZXCT
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Краткое описание:
36M-bit 1.8V Sync SRAM 2M x 18 DDR 0.45ns FBGA
Дополнительная информация
Synchronous SRAM chip, 36M-bit density, organized as 2M words x 18 bits. Features a 0.45 ns maximum access time and operates at a maximum clock rate of 633 MHz with DDR data rate architecture. This surface-mount component is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package, measuring 15mm x 13mm x 0.89mm, with a 1mm pin pitch. It requires a typical operating supply voltage of 1.8V, with a range of 1.7V to 1.9V, and supports a 20-bit address bus.
| PCB | 165 |
| ECCN | 3A991.b.2.a |
| PPAP | No |
| Density | 36Mbit |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Mounting | Surface Mount |
| Cage Code | 65786 |
| Pin Count | 165 |
| Automotive | No |
| Lead Shape | Ball |
| Schedule B | 8542320040 |
| Timing Type | Synchronous |
| Architecture | Pipelined |
| Package/Case | FBGA |
| AEC Qualified | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
| Pin Pitch (mm) | 1 |
| Density in Bits | 37748736bit |
| Number of Ports | 1 |
| Number of Words | 2M |
| Package Material | Plastic |
| Address Bus Width | 20bit |
| Basic Package Type | Ball Grid Array |
| Maximum Clock Rate | 633MHz |
| Package Weight (g) | 0.49956 |
| Package Width (mm) | 13 |
| Maximum Access Time | 0.45ns |
| Package Description | Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 0.89 |
| Package Length (mm) | 15 |
| Data Rate Architecture | DDR |
| Number of Bits per Word | 18bit |
| Seated Plane Height (mm) | 1.4(Max) |
| Max Operating Temperature | 70°C |
| Maximum Operating Current | 965mA |
| Min Operating Temperature | 0°C |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Typical Operating Supply Voltage | 1.8V |
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