DS1100LU-175/T&R
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Краткое описание:
3.3V 5-Tap Silicon Delay Line with 175ns Total Delay
Дополнительная информация
A five-tap, all-silicon CMOS delay line that operates from a 3.0V to 3.6V supply and provides a total delay of 175ns with 35ns spacing between taps. It reproduces both leading and trailing edges of the input waveform with equal precision across the -40°C to +85°C operating temperature range. Each tap can drive up to ten 74LS loads, and the TTL/CMOS-compatible inputs draw negligible leakage current. The low-power device is supplied in an 8-pin µMAX surface-mount package and is vapor-phase and IR solderable.
| RoHS | Not Compliant |
| Total Delay | 175ns |
| Power-Up Time | 200µs |
| Number of Taps | 5 |
| Fan-Out per Tap | 1074LS loads |
| Input Capacitance | 5 typ, 10 maxpF |
| Supply Voltage Range | 3.0 to 3.6V |
| Output Rise/Fall Time | 2.0 typ, 2.5 maxns |
| Nominal Supply Voltage | 3.3V |
| Tap Delays (Tap 1/2/3/4/5) | 35/70/105/140/175ns |
| Operating Temperature Range | -40 to +85°C |
| Low-Level Input Voltage (VIL) | 0.8 maxV |
| High-Level Input Voltage (VIH) | 2.0 minV |
| Low-Level Output Current (IOL) | 8 maxmA |
| High-Level Output Current (IOH) | -1 minmA |
| Active Supply Current (ICC at 1 MHz) | 10mA |
| Delay Tolerance (delays > 40ns, +25°C) | ±5% |
| Delay Tolerance (delays ≤ 40ns, +25°C) | ±2ns |
| Delay Tolerance (delays > 40ns, -40°C to +85°C) | ±13% |
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