EP2AGX125EF29C5NES
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Краткое описание:
FPGA 118K Logic Cells 40nm 780-Pin FC-FBGA 6.375Gbps Transceiver
Дополнительная информация
Field Programmable Gate Array (FPGA) featuring 118,143 logic cells and 8,121 Kbit of RAM. This device operates at 500MHz, built on 40nm process technology, and supports a 0.9V core voltage. It includes 8 transceiver blocks capable of 6.375 Gbps, 72 dedicated DSP blocks, and 32 maximum SERDES channels. The 780-pin FC-FBGA package facilitates surface mounting.
| PCB | 780 |
| ECCN | 3A991 |
| PPAP | No |
| Jedec | MS-034AAM-1 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Mounting | Surface Mount |
| RAM Bits | 8121Kbit |
| Cage Code | 4BA62 |
| Pin Count | 780 |
| Automotive | No |
| Lead Shape | Ball |
| PCI Blocks | 1 |
| Schedule B | 8542390000 |
| Family Name | Arria® II GX |
| Speed Grade | 5 |
| Package/Case | FC-FBGA |
| AEC Qualified | No |
| Dedicated DSP | 72 |
| Ethernet MACs | 1 |
| RoHS Versions | 2011/65/EU |
| Pin Pitch (mm) | 1 |
| Programmability | Yes |
| Package Material | Plastic |
| Supported IP Core | Video LVDS SerDes Transmitter / Receiver|10/100/1G Ethernet MACController (GMAC)|IP Compiler for PCI Express x8 (Soft IP)|Hashing IP Core (BA413)|10/100/1000Mbps Full Duplex Ethernet MAC |
| Transceiver Speed | 6.375Gbps |
| Basic Package Type | Ball Grid Array |
| Device Logic Cells | 118143 |
| Package Width (mm) | 29 |
| Process Technology | 40nm |
| Transceiver Blocks | 8 |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 1.9 |
| Package Length (mm) | 29 |
| Program Memory Type | SRAM |
| Radiation Hardening | No |
| Number of Multipliers | 576 (18x18) |
| Seated Plane Height (mm) | 2.4 |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | 0°C |
| Total Number of Block RAM | 730 |
| Device Number of DLLs/PLLs | 6 |
| Maximum Number of User I/Os | 372 |
| Supported IP Core Manufacture | Microtronix Inc/Mobiveil, Inc/CAST, Inc/Barco Silex/MorethanIP |
| Maximum Number of SERDES Channels | 32 |
| Differential I/O Standards Supported | LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12 |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
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