EP3CLS70F484I7N
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Краткое описание:
FPGA Cyclone III LS, 70K Cells, 65nm, 484-Pin FBGA
Дополнительная информация
Field Programmable Gate Array (FPGA) with 70,208 logic cells and 200 18x18 multipliers, operating at 437.5MHz. This device utilizes 65nm process technology and features 2997 Kbit of RAM bits and 333 total block RAM. It supports a maximum of 278 user I/Os with extensive differential and single-ended I/O standards, including LVPECL, LVDS, LVTTL, and LVCMOS. The FPGA is housed in a 484-pin FBGA package with a 1mm pin pitch, designed for surface mounting. It offers external memory interface support for DDR2 SDRAM and QDRII+ SRAM, and includes 4 DLLs/PLLs.
| PCB | 484 |
| ECCN | 3A991 |
| PPAP | No |
| Jedec | MS-034AAJ-1 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Mounting | Surface Mount |
| RAM Bits | 2997Kbit |
| Cage Code | 4BA62 |
| Pin Count | 484 |
| Automotive | No |
| Lead Shape | Ball |
| Schedule B | 8542390000 |
| Family Name | Cyclone® III LS |
| Speed Grade | 7 |
| Package/Case | FBGA |
| AEC Qualified | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
| Pin Pitch (mm) | 1 |
| Programmability | No |
| Package Material | Plastic |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Basic Package Type | Ball Grid Array |
| Device Logic Cells | 70208 |
| Package Width (mm) | 23 |
| Process Technology | 65nm |
| Package Description | Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 1.5 |
| Package Length (mm) | 23 |
| Program Memory Type | SRAM |
| Radiation Hardening | No |
| Number of Multipliers | 200 (18x18) |
| Seated Plane Height (mm) | 2 |
| External Memory Interface | DDR2 SDRAM|QDRII+SRAM |
| Max Operating Temperature | 100°C |
| Min Operating Temperature | -40°C |
| Total Number of Block RAM | 333 |
| Device Number of DLLs/PLLs | 4 |
| Maximum Number of User I/Os | 278 |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/PLDA |
| Differential I/O Standards Supported | LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL |
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