EP3CLS70U484C8N

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EP3CLS70U484C8N - Intel
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Краткое описание: FPGA 70K Logic Cells 402MHz 65nm 484-Pin UFBGA
Производитель Intel
Статус производства Производится (ACTIVE)

Дополнительная информация

Field Programmable Gate Array (FPGA) with 70,208 logic cells and 200 18x18 multipliers, operating at 402MHz. This device utilizes 65nm process technology and features 2997 Kbit of RAM. It supports up to 278 user I/Os and offers external memory interfaces for DDR2 SDRAM and QDRII+ SRAM. The FPGA is housed in a 484-pin UFBGA package with a 0.8mm pin pitch, designed for surface mounting.
PCB 484
ECCN 3A991
PPAP No
Jedec MO-275PPAA-2
EU RoHS Yes
HTS Code 8542390001
Mounting Surface Mount
RAM Bits 2997Kbit
Cage Code 4BA62
Pin Count 484
Automotive No
Lead Shape Ball
Schedule B 8542390000
Family Name Cyclone® III LS
Speed Grade 8
Package/Case UFBGA
AEC Qualified No
RoHS Versions 2011/65/EU
Pin Pitch (mm) 0.8
Programmability No
Package Material Plastic
Supported IP Core Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Basic Package Type Ball Grid Array
Device Logic Cells 70208
Package Width (mm) 19
Process Technology 65nm
Package Description Ultra Fine Pitch Ball Grid Array
Package Family Name BGA
Package Height (mm) 1.5
Package Length (mm) 19
Program Memory Type SRAM
Radiation Hardening No
Number of Multipliers 200 (18x18)
Seated Plane Height (mm) 1.9
External Memory Interface DDR2 SDRAM|QDRII+SRAM
Max Operating Temperature 85°C
Min Operating Temperature 0°C
Total Number of Block RAM 333
Device Number of DLLs/PLLs 4
Maximum Number of User I/Os 278
Supported IP Core Manufacture Altera/CAST, Inc/Barco Silex/PLDA
Differential I/O Standards Supported LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS
Single-Ended I/O Standards Supported LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL

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