EP4CGX50BF23C8N
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Краткое описание:
FPGA Cyclone IV GX 49888 Cells 60nm 484-Pin FBGA 3.125Gbps Transceivers
Дополнительная информация
Field Programmable Gate Array (FPGA) with 49,888 logic cells and 2.5 Mbit of RAM. This device utilizes 60nm process technology and features 2 Ethernet MACs, 140 multipliers (18x18), and 8 transceiver blocks operating at 3.125 Gbps. It supports a wide range of single-ended and differential I/O standards, external memory interfaces including DDR2 SDRAM and QDRII+ SRAM, and is housed in a 484-pin Fine Pitch Ball Grid Array (FBGA) package for surface mounting. Operating temperature range is 0°C to 85°C.
| PCB | 484 |
| ECCN | 3A991.d |
| PPAP | No |
| Jedec | MS-034AAJ-1 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Mounting | Surface Mount |
| RAM Bits | 2502Kbit |
| Cage Code | 4BA62 |
| Pin Count | 484 |
| Automotive | No |
| Lead Shape | Ball |
| PCI Blocks | 1 |
| Schedule B | 8542390000 |
| Family Name | Cyclone® IV GX |
| Speed Grade | 8 |
| Package/Case | FBGA |
| AEC Qualified | No |
| Ethernet MACs | 2 |
| RoHS Versions | 2011/65/EU |
| Pin Pitch (mm) | 1 |
| Programmability | Yes |
| Package Material | Plastic |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|PCI Express to AXI Bridge Controller (GPEX-PAB)|ISA/PC Card/PCMCIA/Compact Flash Host Adapter |
| Transceiver Speed | 3.125Gbps |
| Basic Package Type | Ball Grid Array |
| Device Logic Cells | 49888 |
| Package Width (mm) | 23 |
| Process Technology | 60nm |
| Transceiver Blocks | 8 |
| Package Description | Fine Pitch Ball Grid Array |
| Package Family Name | BGA |
| Package Height (mm) | 2.2(Max) |
| Package Length (mm) | 23 |
| Program Memory Type | SRAM |
| Radiation Hardening | No |
| Number of Multipliers | 140 (18x18) |
| Seated Plane Height (mm) | 2.6(Max) |
| External Memory Interface | DDR2 SDRAM|QDRII+SRAM |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | 0°C |
| Total Number of Block RAM | 278 |
| Device Number of DLLs/PLLs | 4 |
| Maximum Number of User I/Os | 290 |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc |
| Differential I/O Standards Supported | B-LVDS|HSTL|LVPECL|LVDS|RSDS|SSTL |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL |
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