SN54HC112J
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Краткое описание:
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
Дополнительная информация
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
| RoHS | Not CompliantNo |
| Mount | Through Hole |
| Polarity | Non-Inverting |
| Frequency | 20MHz |
| Lead Free | Contains Lead |
| Packaging | Rail/Tube |
| Technology | CMOS |
| Package/Case | CDIP |
| Max Frequency | 20MHz |
| Logic Function | JK-Type |
| Number of Bits | 2 |
| RoHS Compliant | No |
| Propagation Delay | 245ns |
| Max Supply Voltage | 6V |
| Min Supply Voltage | 2V |
| Number of Elements | 2 |
| Turn-On Delay Time | 245ns |
| Radiation Hardening | No |
| Clock Edge Trigger Type | Negative Edge |
| Low Level Output Current | 5.2mA |
| Operating Supply Voltage | 5V |
| High Level Output Current | -5.2mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
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