SN74S112ADR
Снят с производства
Увеличить
Краткое описание:
Dual J-K Flip-Flop, 125MHz, 5.25V, SOIC, Surface Mount
Дополнительная информация
Dual negative edge-triggered J-K flip-flop with complementary outputs, operating at up to 125MHz. Features a 7ns propagation delay and 4ns turn-on delay. Designed for surface mount with a SOIC package, supporting a supply voltage range of 4.75V to 5.25V. Each circuit offers 20mA high and low level output current. RoHS compliant.
| RoHS | Compliant |
| Mount | Surface Mount |
| Series | 74S |
| Polarity | Non-Inverting |
| Frequency | 125MHz |
| Packaging | Tape and Reel |
| Input Type | SINGLE-ENDED |
| Package/Case | SOIC |
| Logic Function | Flip-Flop |
| Output Current | 20mA |
| RoHS Compliant | Yes |
| Package Quantity | 2500 |
| Propagation Delay | 7ns |
| Max Supply Voltage | 5.25V |
| Min Supply Voltage | 4.75V |
| Number of Circuits | 2 |
| Number of Elements | 2 |
| Turn-On Delay Time | 4ns |
| Number of Input Lines | 5 |
| Number of Output Lines | 2 |
| Clock Edge Trigger Type | Negative Edge |
| Low Level Output Current | 20mA |
| High Level Output Current | 20mA |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Number of Bits per Element | 1 |
Если у вас не открывается документ, нажмите, чтобы открыть файл в новой вкладке.
