STM32U585
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Краткое описание:
160MHz Cortex-M33 MCU, 2MB Flash, 786KB SRAM, ULP, TrustZone, Crypto, rich I/O
Дополнительная информация
Ultra‑low‑power 32‑bit MCU family based on Arm Cortex‑M33 with TrustZone and FPU. Operates to 160MHz with 2MB dual‑bank Flash and up to 786KB SRAM, extensive analog and digital peripherals, advanced security (AES/PKA/TRNG/HUK, SFI, TF‑M), and multiple low‑power modes for IoT, industrial, and consumer applications. Active product line with broad package options (48–169 pins).
| GPIO | Up to 136 I/Os, most 5V‑tolerant; up to 14 I/Os with independent supply down to 1.08V; up to 22 capacitive sensing channelspins |
| RoHS | ECOPACK2 compliant; RoHS grade shown on ST package pages |
| SRAM | Up to 786 (ECC OFF) or 722 (with ECC ON up to 322KB)KB |
| REACH | Distributor environmental docs available (Mouser REACH statement) |
| Analog | 14‑bit ADC @2.5 Msps + 12‑bit ADC @2.5 Msps; 2×12‑bit DAC (LP S/H); 2 op‑amps (PGA); 2 comparators; VREF buffer |
| Clocks | HSE 4–50 MHz; LSE 32.768 kHz; HSI16 ±1%; LSI; multispeed internal up to 48 MHz; internal 48 MHz with CRS; 3 PLLsMHz/kHz |
| Timers | Up to 17 timers total: 2×16‑bit advanced motor‑control, 4×32‑bit, 5×16‑bit GP, 4×16‑bit low‑power, SysTick; 2 watchdogs; RTC |
| CPU core | Arm Cortex‑M33 with TrustZone, FPU, DSP, MPU |
| Graphics | Chrom‑ART Accelerator (DMA2D) and DCMI |
| Packages | UFQFPN48 (7×7), LQFP48/64/100/144 (7×7 to 20×20), UFBGA132/169 (7×7), WLCSP90 (4.2×3.95) |
| Security | Arm TrustZone; secure boot/update; SFI; HDP; unique boot entry; RDP; secure debug unlock; active tamper; 96‑bit UID; 512‑byte OTP |
| RTC backup | VBAT domain with 32×32‑bit backup registers + 2KB backup SRAM |
| Performance | 240 DMIPS; 4.07 CoreMark/MHz (651 total)DMIPS; CoreMark/MHz |
| Flash memory | 2 (dual‑bank, ECC, RWW; 512KB @100k cycles)MB |
| Digital filters | MDF with 6 filters for external Σ‑Δ modulators; ADF with 1 audio filter and sound‑activity detect |
| External memory | FSMC/FMC for SRAM/PSRAM/NOR/NAND/FRAM; 2×Octo‑SPI (≥1 Quad‑SPI on all packages) |
| Longevity program | 10 (marketing commitment; package pages show start 2025‑01‑01)years |
| Math accelerators | CORDIC and FMAC |
| Crypto accelerators | 2×AES (one DPA‑resistant), PKA (DPA‑resistant), HASH, TRNG (NIST SP800‑90B), OTFDEC for Octo‑SPI |
| Max clock frequency | 160MHz |
| Supply voltage range | 1.71 to 3.6V |
| Operating temperature | -40 to +85 (ambient) and -40 to +125 (ambient options; +130 °C junction)°C |
| Security Certification | PSA Certified Level 3 (STM32U585 TFM); SESIP3 |
| Low‑power modes (typ) | Run: 19.5 µA/MHz @3.3V; Stop3: 1.9 µA (16KB SRAM) / 4.3 µA (full SRAM); Stop2: 4.0 µA (16KB) / 8.95 µA (full); Standby: 210 nA (24 WKUP) / 530 nA with RTC; Shutdown: 160 nAµA / µA/MHz / nA |
| Certification (security) | PSA Certified Level 3; SESIP3 (STM32U585 TFM) |
| Communication interfaces | USB OTG FS + USB Type‑C/PD controller; 4×I2C (FM+); 3×SPI (+2 via OCTOSPI +3 via USART); 6×U(S)ART; 2×SAI; 2×SDMMC; 1×FDCAN; PSSI; DCMI |
| Environmental packaging grade | ECOPACK2 (RoHS) |
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