TC74HCT74AF(TP2)
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Краткое описание:
Dual D-Type Flip-Flop with Preset and Clear, 4.5-5.5 V, 14-Pin SOP
Дополнительная информация
High-speed CMOS dual D-type flip-flop with preset and clear, fabricated with silicon-gate C2MOS technology. Each flip-flop transfers the data input to the Q output on the positive edge of the clock, and preset and clear operate independently of the clock when taken low. Running from a 4.5 to 5.5 V supply over -40 to 85 °C, the device accepts TTL, NMOS, and CMOS input levels and drives up to 10 LSTTL loads. Typical maximum clock frequency reaches 53 MHz at 5 V, with a typical CK-to-Q propagation delay of 17 ns and symmetrical 4 mA output drive. The 14-pin SOP package weighs 0.18 g typ., and all inputs include protection circuits against static discharge and transient overvoltage.
| RoHS | Not Compliant |
| Number of Circuits | 2 |
| Output Current (Min) | 4mA |
| Supply Voltage (Max) | 5.5V |
| Supply Voltage (Min) | 4.5V |
| Power Dissipation (SOP) | 180mW |
| Input Capacitance (Typ.) | 5pF |
| Input Rise and Fall Time | 0 to 500ns |
| Storage Temperature Range | -65 to 150°C |
| Operating Temperature (Max) | 85°C |
| Operating Temperature (Min) | -40°C |
| Package Weight (SOP14, Typ.) | 0.18g |
| Low-Level Input Voltage (Max) | 0.8V |
| High-Level Input Voltage (Min) | 2.0V |
| Maximum Clock Frequency (Typ.) | 53MHz |
| Propagation Delay Time CK-Q (Typ.) | 17ns |
| Power Dissipation Capacitance (Typ.) | 32pF |
| Propagation Delay Time CLR/PR-Q (Typ.) | 15ns |
| Quiescent Supply Current (Max, Ta=25°C) | 2µA |
| Maximum Supply Voltage (Absolute Maximum Rating) | 7V |
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